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o ki semiconducto r fedl7021-03 issue date: jun. 1, 2005 m l7021 echo canceler 1 general description the ML7021 is an improved version of the msm7602 with the reduced cancelable echo delay time and additional 2100hz tone detection function. the ML7021 is a low-power cmos device for canceling echo (in an acoustic system or telephone line) generated in a speech path. echo is canceled, in digital signal processing, by estimating the echo path and generating a pseudo echo signal. the ML7021 makes possible a quality conversation by controlling the noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. the devise also controls the low level noise with a center clipping function. further, the ML7021 i/o interface supports m -law pcm . the use of a single chip codec, such as the msm7566/7704 (3 v) or msm7543/7533 (5 v), allows a simplified and efficient echo canceler configuration. features ? tone disable function ? cancelable echo delay time: for a single chip: 8 ms (max.) ? echo attenuation : 30 db (typ.) ? clock frequency : 19.2 mhz external input and internal oscillator circuit are provided. ? power supply voltage : 2.7 v to 5.5 v ? package: 28-pin plastic ssop (ssop28-p-485-0.65-k) (product name : ML7021mb)
2 ? semiconductor ML7021 block diagram howling detector double talk detector power calculator adaptive fir filter (aff) nonClinear/ linear s/p att gain linear/ nonClinear p/s nonClinear/ linear s/p + + C att linear/ nonClinear p/s center clip rin rout sout sin rst v dd v ss wdt p wdwn clock generator mode selector i/o controller int irld sck sync nlp hcl adp att gc synco scko x2 x1/clkin mcko hd 2100hz tone detector
3 ? semiconductor ML7021 pin configuration (top view) 28-pin plastic ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin 1 2 3 4 5 6 7 symbol nlp hcl adp v dd att int irld pin 8 9 10 11 12 13 14 symbol sin rin sck sync sout rout v ss pin 15 16 17 18 19 20 21 symbol v ss hd x1/clkin x2 v dd pwdwn v ss pin 22 23 24 25 26 27 28 symbol synco scko rst wdt gc v dd mcko
4 ? semiconductor ML7021 pin descriptions (1/4) pin symbol type description 1 nlp i 2 hcl i 3 adp i control pin for the center clipping function. this pin forces the sout output to a minimum value when the sout signal is below C54 dbm0. effective for reducing low-level noise. ? single chip or master chip in a cascade connection "h": center clip on "l": center clip off ? slave chip in a cascade connection fixed at "l" this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. through mode control. when this pin is in the through mode, rin and sin data is output to rout and sout. at the same time, the coefficient of the adaptive fir filter is cleared. ? single chip or master chip in a cascade connection "h": through mode "l": normal mode (echo canceler operates) ? slave chip in a cascade connection same as the master chip this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. aff coefficient control. this pin stops updating of the adaptive fir filter (aff) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. this pin is used when holding the aff coefficient which has been once converged. ? single chip or master chip in a cascade connection "h": coefficient fix mode "l": normal mode (coefficient update) ? slave chip in a cascade connection fixed at "l" this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal.
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6 ? semiconductor ML7021 (3/4) pin symbol type description 11 sync i 12 sout o 13 rout o 17 x1/clkin i 18 x2 o 16 hd i sync signal for transmit/receive serial data. this pin uses the external sync or synco. input the pcm codec transmit/receive sync signal (8 khz). transmit serial data. outputs the pcm signal synchronized to sync and sck. this pin is in a high impedance state during no data output. receive serial data. outputs the pcm signal synchronized to sync and sck. this pin is in a high impedance state during no data output. controls the howling detect function. this pin detets and cancels a howling generated during hand-free talking for acoustic system. this function is used to cancel acoustic echoes. ? single chip or master chip in a cascade connection "l": howling detector on "h": howling detector off ? slave chip in a cascade connection fixed at "l" external input for the basic clock (17.5 to 20 mhz) or for the crystal oscillator. when the internal sync signal (synco, scko) is used, input the basic clock of 19.2 mhz. crystal oscillator output. used to configure the oscilation circuit. refer to the internal clock generator circuit example. when inputting the basic clock externally, insert a 5 pf capacitor with excellent high frequency characteristics between x2 and gnd. 20 pwdwn i power-down mode control when powered down. "l": power-down mode "h": normal operation mode during power-down mode, all input pins are disabled and output pins are in the following states : high impedance : sout, rout "l": synco, scko, mcko "h": of1 , of2 , x2 holds the last state : wdt, irld reset after the power-down mode is released.

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1 semiconductor ML7021 10 ac characteristics parameter clock frequency when internal sync signal is not used clock cycle time when internal sync signal is not used clock duty ratio clock high level pulse width fc = 19.2 mhz clock low level pulse width fc = 19.2 mhz clock rise time clock fall time sync clock output time internal sync clock frequency internal sync clock output cycle time internal sync clock duty ratio internal sync signal output delay time internal sync signal period internal sync signal output width transmit/receive operation clock frequency transmit/receive sync clock cycle time transmit/receive sync clock duty ratio transmit/receive sync signal period sync timing sync signal width receive signal setup time receive data input time irld signal output delay time serial output delay time symbol f c t mck t dmc t mch t mcl t r t f t dcm f co t co t dco t dcc t cyo t wso f sck t sck t dsc t cyc t xs t sx t wsy t ds t id t dic t wir t sd t xd t wr min. 17.5 50 40 20.8 20.8 64 0.488 40 123 45 t sck 1 typ. 19.2 52.08 256 3.9 50 125 t co 50 125 7t sck t sck max. 20 57.14 60 31.3 31.3 2048 15.6 60 min. 17.5 50 40 20.8 20.8 64 0.488 40 123 45 45 t sck 45 1 typ. 19.2 52.08 256 3.9 50 125 t co 50 125 7t sck t sck max. 20 57.14 60 31.3 31.3 5 5 30 5 2048 15.6 60 138 90 90 unit mhz ns ns ns ns ns ns ns khz m s % ns m s m s khz m s % m s ns ns m s ns m s ns m s ns ns m s v dd = 2.7 v to 3.6 v v dd = 4.5 v to 5.5 v (ta = C40?c to +85?c) reset start time t drs 5ns reset end time t dre 52ns processing operation start time t dit 100 100 m s irld signal output width reset signal input width 30 5 5 5 45 45 138 5 90 90 52 receive signal hold time t dh 45ns 45 t cyc -t sck t cyc -t sck ? ?
11 ? semiconductor ML7021 ac characteristics (continued) parameter power down start time power down end time control pin setup time ( int ) control pin hold time ( int ) symbol t dps t dts t dth min. typ. max. min. 20 120 typ. max. 111 15 unit ns ns ns v dd = 2.7 v to 3.6 v v dd = 4.5 v to 5.5 v (ta = C40?c to +85?c) t dpe ns control pin hold time ( rst )t dhr 10 ns control pin setup time ( rst )t dsr 20 ns 10 20 120 20 15 111
12 ? semiconductor ML7021 timing diagram clock timing x1/clkin t r t f t mch t mcl f c , t mck , t dmc scko t dcm scko synco t cyo t dco t dcc t dcc t wso f co , t co t dcm serial input timing sck sync sin rin msb 7 t cyc f sck , t sck t sx t xs t wsy t dh t ds 654321 lsb 0 msb 7 t dsc irld t id t dic t dic t wir
13 ? semiconductor ML7021 serial output timing operation timing after reset power down timing t dps t dpe internal operation processing start power down p wdwn sck sync sout rout msb 7 t cyc f sck , t sck t sx t xs t wsy t sd 654321 lsb 0 msb 7 t dsc high-z t xd t xd high-z t xd t drs rst t wr t dre internal operaion processing start t dit reset initialization *reset timing can be asynchronous note: int is invalid in the diagonally shaded interval.
14 ? semiconductor ML7021 control pin load-in timing int ( irld ) *t cyc nlp, hcl, hd, att, adp, gc t dhr rst t wr t dsr nlp, hcl, hd, att, adp, gc t dth t dts *for irld output timing, refer to serial input timing
15 ? semiconductor ML7021 how to use the ML7021 the ML7021 cancels (based on the rin signal) the echo which returns to sin. connect the base signal to the r side and the echo generated signal to the s side. connection methods according to echos example 1: canceling acoustic echo (to handle acoustic echo from line input) + + C aff rout sin rin sout ML7021 codec codec h line input acoustic echo example 2: canceling line echo (to handle line echo from microphone input) + + C aff rin sout rout sin ML7021 h line echo microphone input codec codec
16 ? semiconductor ML7021 internal clock generator circuit example ML7021 x1/clkin x2 xtal r c1 c2 r xtal c1 c2 gnd gnd : 19.2 mhz : 1 m w : 27 pf : 27 pf external clock input circuit example ML7021 x1/clkin x2 clk 5pf gnd

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18 ? semiconductor ML7021 measurement system block diagram rin sout rout sin ML7021 msm7543 m -law codec msm7543 m -law codec delay t d echo delay time att erl (echo return loss) power supply voltage 5 v rin sout l. p. f. 5 khz level meter white noise generator a a pcm pcm pcm pcm a a
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20 ? semiconductor ML7021 notes on use 1. set echo return loss (erl) to be attenuated. if the echo return loss is set to be amplified, the echo can not be eliminated. refer to the characteristic diagram for erl vs. echo attenuation quantity. 2. set the level of the analog input so that the pcm codec does not overflow. 3. the recommended input level is C10 to C20 dbm0. refer to the characteristic diagram for the rin input level vs. echo attenuation quantity. 4. applying the tone signal to this echo canceler for long duration may decrease echo attenuation. when used with the hd pin "l" (howling detector on), this echo canceler may operate faultily if, while a signal is input to the rin pin, a tone signal with a higher level than the signal being input to rin is input to the sin pin. a signal should therefore be input either to the rin pin or to the sin pin. if, however, the tone signal is input to the sin pin while a signal is input to the rin pin, the adp, hd, or hcl pin must be set to "h". 5. for changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. perform a reset, to make it converge. if the state of the echo path changes after a reset, convergence may again be difficult. in cases such as a change in the echo path, perform a reset each time. 6. when turning the power on, set the pwdwn pin to "1" and input the basic clock simultaneously with power on. if powering down immediately after power on, be sure fast input 10 or more clocks of the basic clock. 7. after powering on, be sure to reset. 8. after the power down mode is released (when the pwdwn pin is changed from "l" to "h"), be sure to reset the device. 9. if this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 db.

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1 semiconductor ML7021 22 package dimensions (unit : mm) i ini mti m mti in ttmnt it () i ti nt t t i in tin ( m m) t ntin t nt mnt t ti t t in mntin n miit in t m mntin ntt i ni n t t nm nm in nm n i mntin nitin ( mt tmt n tim)
1 semiconductor ML7021 23 revision history page document no. date previous edition current edition description fedl7021-02 nov. 2001 ? ? final edition 2 fedl7021-03 jun. 1, 2005 10 10 revised max. values of ?sync timing? and ?sync signal width? in the table in the ?ac characteristics? section.
1 semiconductor ML7021 24 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifically authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and n ecessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2005 oki electric industry co., ltd.

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